A. Field of the Invention
The present invention relates to a semiconductor device and a semiconductor device fabrication method.
B. Description of the Related Art
In a general planar n-channel vertical metal oxide semiconductor field effect transistor (MOSFET: insulated gate field effect transistor), among a plurality of semiconductor layers formed in a semiconductor substrate, an n− drift layer is a semiconductor layer with the highest resistance. When the thickness of the n− drift layer is reduced to shorten a current path, the resistance of the semiconductor layer with high resistance is reduced. Therefore, the overall on-resistance of the MOSFET is substantially reduced.
However, in the off state of the MOSFET, a depletion layer spreads to the n− drift layer with high resistance and the breakdown voltage is maintained by the spreading of the depletion layer. Therefore, when the thickness of the n− drift layer is reduced, the spreading of the depletion layer is reduced and electric field intensity is likely to reach a critical value at a low applied voltage. As a result, the breakdown voltage is reduced. In contrast, a MOSFET with a high breakdown voltage requires a thick n− drift layer. Therefore, on-resistance increases and electrical connection loss increases. The relationship between the on-resistance and the breakdown voltage is called a trade-off relation. In general, it is difficult to increase the on-resistance and the breakdown voltage having the trade-off relationship therebetween.
It has been known that there also is a trade-off relationship between the on-resistance and the breakdown voltage in a bipolar power semiconductor device, such as an insulated gate bipolar transistor (IGBT), a bipolar transistor, or a diode. As a device which improves the trade-off relationship to increase the on-resistance and to increase the breakdown voltage, a semiconductor device with a super junction (SJ) structure (hereinafter, referred to as a super junction semiconductor device) has been proposed in which a drift layer is a parallel pn layer in which a n-type region and a p-type region with high impurity concentration are alternately arranged.
FIG. 11 illustrates a portion of a super junction MOSFET 100 as an example of the super junction semiconductor device. FIG. 11 is a perspective view illustrating the structure of the super junction MOSFET according to the related art. Hereinafter, the structure of the super junction MOSFET 100 according to the related art will be described. The super junction MOSFET 100 according to the related art includes a drift layer with a higher impurity concentration than a drift layer of a general MOSFET which has the same breakdown voltage as the super junction MOSFET 100. The drift layer is a parallel pn layer 20 having the following structure: an n-type region 1 and a p-type region 2, in which a width in a direction parallel to the main surface of a substrate is less than a length (depth) in a direction perpendicular to the main surface of the substrate, are alternately arranged in the direction parallel to the main surface of the substrate so as to come into contact with each other; and a plurality of pn junctions formed between the two regions are arranged in the direction perpendicular to the main surface of the substrate. The width of the n-type region 1 and the p-type region 2 is set to a value which enables a depletion layer to be spread from the pn junction into each region when a low reverse bias voltage (100 V to 200 V) is applied to the pn junction between the two regions.
The super junction MOSFET 100 has the same layer structure as a general MOSFET except for the parallel pn layer 20. In the layer structure, for example, a p base region 3, an n-type surface region 4, a p+ contact region 5, an n+ source region 6, a gate insulating film 7, a gate electrode 8, an interlayer insulating film 9, and a source electrode 10 are provided as a front-surface-side structure. A drain electrode 12 which comes into contact with a n+ drain layer 11 is provided as a rear-surface-side structure (for example, see U.S. Pat. No. 5,216,275 (FIGS. 1 to 5), U.S. Pat. No. 5,438,215 (FIG. 1), and JP 9-266311 A (FIGS. 7 to 9)). As illustrated in FIG. 11, the n-type region 1 forming the parallel pn layer 20 is obtained by laminating an n-type low-concentration region 22, an n-type high-concentration region 21, and an n-type surface region 4 from the rear surface. Similarly, the p-type region 2 is obtained by laminating a p-type low-concentration region 24 and a p-type high-concentration region 23 from the rear surface.
FIG. 2 is a plan view illustrating a planar pattern in a cut surface when a lower end portion of the parallel pn layer illustrated in FIG. 11 (a portion of the parallel pn layer 20 close to the rear surface of the substrate) is cut along the line E1-E2 parallel to the main surface of the substrate. FIG. 2 illustrates that the n-type region 1 and the p-type region 2 of the parallel pn layer 20 are formed in parallel with the same pattern width in the depth direction of the plane of paper which is not illustrated in FIG. 11.
FIG. 3 is a characteristic diagram illustrating an impurity concentration distribution in a cut surface taken along the line C1-C2 and the line D1-D2 of FIG. 11. The cut surface taken along the line C1-C2 and the line D1-D2 is perpendicular to the main surface of the substrate and the depth direction of the plane of paper. The impurity concentration distribution of the n-type region (solid line) illustrated in FIG. 3 is an n-type impurity concentration distribution in a direction which is perpendicular to the main surface of the substrate and corresponds to the line A1-A2 of FIG. 11. The impurity concentration distribution of the p-type region (dotted line) illustrated in FIG. 3 is a p-type impurity concentration distribution in a depth direction from the front surface of a semiconductor substrate which corresponds to the line B1-B2 of FIG. 11.
In FIG. 3, the vertical axis indicates an impurity concentration and the horizontal axis indicates the depth from the front surface of the substrate. In FIG. 3, a first depth d0 is the depth from the upper end of the p base region 3 (the front surface of the substrate) to the bottom of the p base region 3 (an interface between the p base region 3 and the p-type high-concentration region 23). The p-type impurity concentration distribution up to the first depth d0 from the front surface of the substrate is a two-stage p-type impurity concentration distribution (dotted line) of the first p+ contact region 5 and the p base region 3. A second depth d1 is the depth from the bottom of the p base region 3 to the lower end (an end close to the rear surface of the substrate, that is, an interface between the n-type high-concentration region 21 and the n-type low-concentration region 22) of the n-type high-concentration region 21 adjacent to the p-type high-concentration region 23 which is a layer below the p base region 3 (a layer close to the rear surface of the substrate). A third depth d2 is the depth to the lower end (an end close to the rear surface of the substrate) of the p-type low-concentration region 24 which is arranged at the lower end of the n-type high-concentration region 21.
As illustrated in FIG. 3, in the n-type impurity concentration distribution (solid line) along the line A1-A2, the impurity concentration distribution of the n-type low-concentration region 22 below the lower end of the n-type high-concentration region 21 is the same as the impurity concentration distribution of the original semiconductor substrate and is uniform. However, the impurity concentration distribution may have gradient impurity concentration. The original semiconductor substrate means a semiconductor substrate before the parallel pn layer 20 is formed. In addition, the n-type high-concentration region 21 and the n-type surface region 4 are formed as layers (layers close to the front surface of the substrate) above the n-type low-concentration region 22. As such, it is preferable that the n-type region 1 have a three-stage impurity concentration distribution in which the n-type low-concentration region 22, the n-type high-concentration region 21, and the n-type surface region 4 have different impurity concentrations. In the three-stage impurity concentration distribution, preferably, the n-type low-concentration region 22, which is the lowest layer of the n-type region 1, has the lowest impurity concentration, followed by the n-type high-concentration region 21 and the n-type surface region 4. The n-type high-concentration region 21 and the n-type surface region 4 may have the same impurity concentration.
As described above, the p-type impurity concentration distribution (dotted line) along the line B1-B2 is a four-stage impurity concentration distribution including the two-stage impurity concentration distribution of the p+ contact region 5 and the p base region 3 and the two-stage impurity concentration distribution of the p-type high-concentration region 23 which is represented by the second depth d1 from the bottom of the p base region 3 and the p-type low-concentration region 24 which is represented by the third depth d2 from the lower end of the p-type high-concentration region 23. In this case, as illustrated in FIG. 3, it is desirable that the p-type high-concentration region 23 which is represented by the second depth d1 from the bottom of the p base region 3 have a higher high impurity concentration than the p-type low-concentration region 24 which is represented by the third depth d2 from the lower end of the p-type high-concentration region 23 (the lower end of the n-type high-concentration region 21). As illustrated in FIGS. 3 and 11, it is preferable that a region which includes the p+ contact region 5 and the p base region 3 and is represented by the first depth d0 from the front surface of the substrate be deeper than the n-type surface region 4.
In the super junction MOSFET 100 having the above-mentioned structure, even when the impurity concentration of the parallel pn layer 20 is higher than that of the drift layer of the general MOSFET that has the same breakdown voltage as the parallel pn layer 20, the depletion layer is spread from each pn junction, which extends in the vertical direction (the direction perpendicular to the main surface of the substrate) between the parallel pn layers 20, into each parallel pn layer 20 in the horizontal direction (the direction parallel to the main surface of the substrate) at a low breakdown voltage in an off state and the entire drift layer is rapidly depleted. Therefore, it is possible to increase the breakdown voltage. In addition, since the drift layer has high impurity concentration, on-resistance is reduced.
In many cases, the power MOSFET is used as a switching device. Therefore, both electrical connection loss which occurs in an on state and switching loss which occurs during switching need to be reduced. One of the main causes of an increase in switching loss is turn-off loss. For example, the time rate of change of the drain voltage (hereinafter, referred to as turn-off dv/dt) when the semiconductor device is turned off may increase to reduce the turn-off loss. However, when the turn-off dv/dt increases, noise is likely to be generated. It is necessary to reduce the turn-off dv/dt in order to reduce noise. As such, the trade-off relationship is generally established between the turn-off loss and the turn-off dv/dt.
For example, when the turn-off dv/dt is 10 kV/μs at which no noise is generated, the turn-off loss is about 0.5 mJ in the super junction MOSFET according to the related art and is about 0.1 mJ in the general MOSFET. That is, in the super junction MOSFET according to the related art, the deterioration of the trade-off relationship between the turn-off loss and the turn-off dv/dt is about five times more than that in the general MOSFET according to the related art. Therefore, for example, even though on-resistance can be reduced to about one fifth, the effect of reducing total loss by the super junction MOSFET is substantially cancelled. As such, in the super junction MOSFET according to the related art, even when the trade-off relationship between the on-resistance and the breakdown voltage can be improved, the trade-off relationship between the turn-off loss and the turn-off dv/dt deteriorates.
In the super junction MOSFET according to the related art, in the case in which the charge balance of the parallel pn layer is under the charge balance condition that the breakdown voltage is at the highest level, when an avalanche current between the drain and the source increases, the drain voltage is reduced. Therefore, when an avalanche occurs, negative resistance is generated and the avalanche current is likely to be locally concentrated. As a result, avalanche current breakdown resistance (hereinafter, referred to as avalanche resistance) is reduced. In order to solve the problem, a technique has been known in which a p-type region forming a parallel pn layer is provided closer to the rear surface of a substrate than an n-type region forming the parallel pn layer and the amount of p-type impurities on the front surface side of the parallel pn layer is more than the amount of n-type impurities, thereby reducing the negative resistance of current-voltage during avalanche and improving avalanche resistance (for example, see PCT International Publication No. WO 2011-93473 (paragraphs 0021 and 0022)).
In addition, a technique has been proposed which relates to a reduction in avalanche resistance due to the turn-on of a parasitic bipolar transistor in a super junction MOSFET according to the related art (for example, see the following JP 2011-3609 A (paragraph 0004)). Furthermore, the following has been proposed in which, in the super junction MOSFET according to the related art, when a reverse bias is applied to a pn junction, a large amount of avalanche current flows and negative resistance is generated, which results in a reduction in avalanche resistance (for example, see JP 2009-188177 A (paragraph 0013)).
As another structure of the super junction MOSFET according to the related art, the following structure has been proposed. The impurity concentration of a p-type region and an n-type region of a parallel pn layer increases stepwise from the rear surface of a substrate in a substantially vertical direction (to the front surface of the substrate). In particular, when the impurity concentration of the p-type region and the n-type region of the parallel pn layer increases in three or more steps in the substantially vertical direction, a semiconductor element with low on-resistance and a high breakdown voltage is obtained. In addition, the impurity concentration of the p-type region and the n-type region of the parallel pn layer is not changed stepwise, but may be changed continuously or in a wave shape in the depth direction (the direction perpendicular to the main surface of the substrate). The impurity concentration of the p-type region and the lower end of the n-type region of the parallel pn layer is preferably higher than that of an n− semiconductor layer (drift layer) (for example, see JP 2008-91450 A (paragraph 0017)).
As another structure of the super junction MOSFET according to the related art, the following structure has been proposed. A charge unbalance margin means that the amount of charge represented by the product of the carrier concentration and width of an n-type region of a parallel pn layer is equal to the amount of charge represented by the product of the carrier concentration and width of a p-type region of the parallel pn layer. In other words, the charge unbalance margin is the design allowable values of the carrier concentration and width of the p-type region and the n-type region of the parallel pn layer in the range in which the breakdown voltage is not reduced, with respect to deviation from the ideal amount of charge of the parallel pn layer which can completely deplete the parallel pn layer. A technique has been proposed in which the charge unbalance margin is preferably equal to or greater than ±15%, considering various variations in a process of fabricating a power MOSFET (for example, see JP 2006-66421 A (paragraphs 0010 and 0011)).
When the parallel pn layer forming the drift layer of the super junction MOSFET has the structure disclosed in the above-mentioned PCT International Publication No. WO 2011-93473, it is possible to prevent the generation of negative resistance and positive resistance characteristics are obtained as in the general MOSFET including a single drift layer. Therefore, avalanche resistance is improved. However, in the structure disclosed in the above-mentioned PCT International Publication No. WO 2011-93473, a portion with high electric field intensity is distributed along each pn junction between the parallel pn layers in the super junction structure. In addition, a p base region 3, an n+ source region 6, and a p+ contact region 5 are provided immediately above (on the front surface side of the substrate) the parallel pn layer in a stripe shape that extends along the same direction as the direction in which the stripe pattern of the pn junction of the parallel pn layer extends. Therefore, when an avalanche current flows through the p-type base region 3, it flows to a source electrode 10 through the vicinity of a portion which is arranged immediately below the n+ source region 6 (the vicinity of a portion of the p-type base region 3 interposed between the n+ source region 6 and the p-type region 2). As a result, the avalanche current becomes a base current of the parasitic bipolar transistor (the n-type surface region 4-the p-type base region 3−the n+ source region 6 in FIG. 11) and the parasitic bipolar transistor operates and is likely to be broken.
The invention has been made in order to solve the above-mentioned problems and an object of the invention is to provide a semiconductor device and a semiconductor device fabrication method which can improve avalanche resistance.